Title:   "Advanced Packaging Technology Solutions for Today's Leading Edge Microelectronics"
with Charles G. Woychik, Ph.D, GE Global Research

Please Post and Circulate, through Oct. 1, 2007

LOCATION:
Holiday Inn San Jose
1740 North First Street, San Jose

SPONSOR:
The Institute of Electrical and Electronics Engineers: the Components, Packaging, and Manufacturing Technology Society Chapter.

COST:
IEEE Members: $300 for half-day Course; $450 for full day (2 Courses)
Non-Members: $350 for half-day Course, $500 for full day (2 Courses)
See descriptions of all 7 Courses in the Advance Program.
REGISTER at our on-line registration site, or use the printed Symposium Advance Program form.

OVERVIEW:
This presentation will explore advanced packaging solutions for next generation microelectronics by looking at three key applications areas that are driving the packaging and interconnection developments. We will look at technology trends, market segments, application requirements, packaging approaches and electronic material developments.

Semiconductor device trends in I/O count, power, bias voltage, and clock rate are driving advanced packaging needs. Three key electronics market segments – Cost-Performance Electronics, Portable Electronics and Automotive Electronics –are driving packaging developments. We will look at the unique needs and characteristics of these market segments and the latest packaging advancements each segment drives.

After analyzing wire bond vs flip chip, area array packages vs leaded carriers, and BGA vs Chip Scale and Flip Chip, we examine trends in high density interconnect structures, optical interconnections, integrated passives and 3-D electronics. The special packaging needs for MEMS devices will also be covered, the changing environmental requirements such as lead free on packages, assembly and materials,and critical materials developmental needs in thermal interface materials, underfill materials, molding and protective materials. This presentation will cover examples of advanced packaging developments currently underway at GE Global Research.

Course Outline:

Objective Evolving Microelectronics Arena Semiconductor Trends Key Electronics Market Segments Advanced Pkgng Trends Cost-Performance Electronics Multichip Technologies Portable Electronics Flip Chip and Chip Scale Electrical/Optical Interconnects

Automotive Electronics Interconnection Structures Integral Passives Optical Interconnects 3-D Electronics MEMS Packaging LEDs and OLEDs • Electronic Materials Opportunities Underfill Developments Thermal Interface Developments

Intended Audience
This tutorial is targeted at new entrants into the packaging and interconnection field, suppliers of materials, components and equipment to the microelectronics fabrication and assembly industry and to users of electronics. It provides a strong historical background on the microelectronics industry; and shows the attendee where packaging and interconnection are today and where they are going.

ABOUT THE INSTRUCTOR:
Charles G. Woychik received his Ph.D. in Materials Science and Engineering from Carnegie-Mellon University in 1984. He joined IBM in Endicott, NY working in the area of soldering and materials selection for electronics packaging. He has held both technical and managerial positions at IBM during his 18 year career. In 2002, he joined Advanced Semiconductor Engineering (ASE) Inc., and had the position of Director of Engineering and Technical Programs. In 2004 he joined Plexus Corporation where he had the responsibility to lead the Microelectronics organization. In 2005 he joined GE Global Research where he is currently involved in the development of electronic packages for healthcare diagnostics applications.