Title:   "Implementing Flip Chip and WLP Technology"
with Peter Elenius, E&G Technology Partners

Please Post and Circulate, through Oct. 1, 2007

LOCATION:
Holiday Inn San Jose
1740 North First Street, San Jose

SPONSOR:
The Institute of Electrical and Electronics Engineers: the Components, Packaging, and Manufacturing Technology Society Chapter.

COST:
IEEE Members: $300 for half-day Course; $450 for full day (2 Courses)
Non-Members: $350 for half-day Course, $500 for full day (2 Courses)
See descriptions of all 7 Courses in the Advance Program.
REGISTER at our on-line registration site, or use the printed Symposium Advance Program form.

OVERVIEW:
This course focuses on the implementation of flip chip (FC) and wafer level packaging (WLP) bumping technologies. The course material covers the selection of the appropriate technology, the processes used and challenges encountered in the deployment of flip chip and wafer level package manufacturing.

Course Outline:

• What drives flip chip (FC) and wafer level package (WLP) adoption.
• Common FC and WLP bump structures including a review of the Intel Cu-Post technology.
• Overview of FC and WLP bumping processes, materials and equipment.
• Available solder alloys, including benefits, drawbacks and how to choose.
• Processing issues that impact yield.
• Reliability failure mechanisms, including thermal cycle, electromigration and diffusion.
• Failure analysis techniques to identify processing issues and reliability failures.

Intended Audience
Target audience includes individuals and companies currently using or considering the use and/or deployment of FC or WLP technology. Especially beneficial to those outsourcing their production, the course provides a fundamental understanding of the technology options available, the processes employed and relevant issues that arise.

ABOUT THE INSTRUCTOR:
A founder and managing partner at E&G Technology Partners (a firm specializing in technology commercialization and business development), Peter Elenius's experience with Flip Chip and WLP technologies spans more than 25 years. He helped establish Flip Chip Technologies (FCT) where he served as VP of Technology and CTO. Prior to FCT he worked at Kulicke & Soffa and IBM in flip chip related technologies. Recognized world wide as an expert in flip chip and wafer-level packaging technologies, Peter speaks at numerous conferences, publishes a wide range of papers and holds ten patents in the field of advanced packaging. Peter earned an MS degree in Manufacturing Systems and a BS in Mechanical Engineering from the University of Wisconsin – Madison before entering the industry at IBM.